Clock data recovery (CDR) is an important block in a receiver system for high-speed serial communications. The CDR block generates the correct sampling dock phase for data recovery. The quality of the high-speed serial communication link can be sensitive to the sampling dock phase, especially in the presence of jitter and noise.
In a receiver having a phase interpolator that determines a clock phase for sampling the incoming data, the CDR is used to identify if the currently used dock phase is the best to capture the incoming data. The CDR provides dynamic phase adjustments for the phase interpolator. The CDR operates to move the dock phase location towards the center of the data eye. The farther the current dock phase is from the center of the data eye the longer it takes for the CDR to lock to the correct dock phase. Long locking times can lead to data loss.